xive_opsRegular
4.4: Absent ⚠️
4.8: Absent ⚠️
4.10: Absent ⚠️
4.13: Absent ⚠️
4.15: Absent ⚠️
4.18: Absent ⚠️
5.0: Absent ⚠️
5.3: Absent ⚠️
5.4: Absent ⚠️
5.8: Absent ⚠️
5.11: Absent ⚠️
5.13: Absent ⚠️
5.15: Absent ⚠️
5.19: Absent ⚠️
6.2: Absent ⚠️
6.5: Absent ⚠️
6.8: Absent ⚠️
arm64: Absent ⚠️
armhf: Absent ⚠️
ppc64el: ✅struct xive_ops {
int (*populate_irq_data)(u32, struct xive_irq_data *);
int (*configure_irq)(u32, u32, u8, u32);
int (*get_irq_config)(u32, u32 *, u8 *, u32 *);
int (*setup_queue)(unsigned int, struct xive_cpu *, u8);
void (*cleanup_queue)(unsigned int, struct xive_cpu *, u8);
void (*setup_cpu)(unsigned int, struct xive_cpu *);
void (*teardown_cpu)(unsigned int, struct xive_cpu *);
bool (*match)(struct device_node *);
void (*shutdown)();
void (*update_pending)(struct xive_cpu *);
void (*eoi)(u32);
void (*sync_source)(u32);
u64 (*esb_rw)(u32, u32, u64, bool);
int (*get_ipi)(unsigned int, struct xive_cpu *);
void (*put_ipi)(unsigned int, struct xive_cpu *);
const char *name;
};
riscv64: Absent ⚠️
aws: Absent ⚠️
azure: Absent ⚠️
gcp: Absent ⚠️
lowlatency: Absent ⚠️
Arch