website-struct

Struct: pcie_port

Status

Regular

• In 4.4: Absent ⚠️
• In 4.8: ✅

  struct pcie_port {
      struct device *dev;
      u8 root_bus_nr;
      void *dbi_base;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      u32 lanes;
      struct pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      long unsigned int msi_data;
      long unsigned int msi_irq_in_use[1];
  };
  

• In 4.10: ✅

  struct pcie_port {
      struct device *dev;
      u8 root_bus_nr;
      void *dbi_base;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      u32 lanes;
      u32 num_viewport;
      struct pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      long unsigned int msi_data;
      u8 iatu_unroll_enabled;
      long unsigned int msi_irq_in_use[1];
  };
  

• In 4.13: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      long unsigned int msi_data;
      long unsigned int msi_irq_in_use[1];
  };
  

• In 4.15: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      long unsigned int msi_data;
      long unsigned int msi_irq_in_use[1];
  };
  

• In 4.18: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      u32 num_vectors;
      u32 irq_status[8];
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.0: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      u32 num_vectors;
      u32 irq_status[8];
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.3: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.4: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.8: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.11: ✅

  struct pcie_port {
      bool has_msi_ctrl;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      u16 msi_msg;
      dma_addr_t msi_data;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_host_bridge *bridge;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.13: ✅

  struct pcie_port {
      bool has_msi_ctrl;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      u16 msi_msg;
      dma_addr_t msi_data;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_host_bridge *bridge;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.15: ✅

  struct pcie_port {
      bool has_msi_ctrl;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      u16 msi_msg;
      dma_addr_t msi_data;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_host_bridge *bridge;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 5.19: ✅

  struct pcie_port {
      bool has_msi_ctrl;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      u16 msi_msg;
      dma_addr_t msi_data;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_host_bridge *bridge;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In 6.2: Absent ⚠️
• In 6.5: Absent ⚠️
• In 6.8: Absent ⚠️

Arch

• In arm64: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In armhf: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[8];
  };
  

• In ppc64el: Absent ⚠️
• In riscv64: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

Flavor

• In aws: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In azure: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In gcp: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

• In lowlatency: ✅

  struct pcie_port {
      u8 root_bus_nr;
      u64 cfg0_base;
      void *va_cfg0_base;
      u32 cfg0_size;
      u64 cfg1_base;
      void *va_cfg1_base;
      u32 cfg1_size;
      resource_size_t io_base;
      phys_addr_t io_bus_addr;
      u32 io_size;
      u64 mem_base;
      phys_addr_t mem_bus_addr;
      u32 mem_size;
      struct resource *cfg;
      struct resource *io;
      struct resource *mem;
      struct resource *busn;
      int irq;
      const struct dw_pcie_host_ops *ops;
      int msi_irq;
      struct irq_domain *irq_domain;
      struct irq_domain *msi_domain;
      dma_addr_t msi_data;
      struct page *msi_page;
      struct irq_chip *msi_irq_chip;
      u32 num_vectors;
      u32 irq_mask[8];
      struct pci_bus *root_bus;
      raw_spinlock_t lock;
      long unsigned int msi_irq_in_use[4];
  };
  

Differences

Regular

• Changed between 4.8 and 4.10 ⚠️

  • Field added. u32 num_viewport
  • Field added. u8 iatu_unroll_enabled
• Changed between 4.10 and 4.13 ⚠️

  • Field removed. struct device *dev
  • Field removed. void *dbi_base
  • Field removed. u32 lanes
  • Field removed. u32 num_viewport
  • Field removed. u8 iatu_unroll_enabled
  • Field type changed. struct pcie_host_ops *ops ➡️ const struct dw_pcie_host_ops *ops
• No changes between 4.13 and 4.15 ✅
• Changed between 4.15 and 4.18 ⚠️

  • Field added. struct irq_domain *msi_domain
  • Field added. u32 num_vectors
  • Field added. u32 irq_status[8]
  • Field added. raw_spinlock_t lock
  • Field type changed. long unsigned int msi_data ➡️ dma_addr_t msi_data
  • Field type changed. long unsigned int msi_irq_in_use[1] ➡️ long unsigned int msi_irq_in_use[4]
• No changes between 4.18 and 5.0 ✅
• Changed between 5.0 and 5.3 ⚠️

  • Field added. struct page *msi_page
  • Field added. struct irq_chip *msi_irq_chip
  • Field added. u32 irq_mask[8]
  • Field added. struct pci_bus *root_bus
  • Field removed. u32 irq_status[8]
• No changes between 5.3 and 5.4 ✅
• No changes between 5.4 and 5.8 ✅
• Changed between 5.8 and 5.11 ⚠️

  • Field added. bool has_msi_ctrl
  • Field added. u16 msi_msg
  • Field added. struct pci_host_bridge *bridge
  • Field removed. u8 root_bus_nr
  • Field removed. u64 cfg1_base
  • Field removed. void *va_cfg1_base
  • Field removed. u32 cfg1_size
  • Field removed. u64 mem_base
  • Field removed. phys_addr_t mem_bus_addr
  • Field removed. u32 mem_size
  • Field removed. struct resource *cfg
  • Field removed. struct resource *io
  • Field removed. struct resource *mem
  • Field removed. struct resource *busn
  • Field removed. struct page *msi_page
  • Field removed. struct pci_bus *root_bus
• No changes between 5.11 and 5.13 ✅
• No changes between 5.13 and 5.15 ✅
• No changes between 5.15 and 5.19 ✅

Arch

• No changes between amd64 and arm64 ✅
• Changed between amd64 and armhf ⚠️

  • Field type changed. long unsigned int msi_irq_in_use[4] ➡️ long unsigned int msi_irq_in_use[8]
• No changes between amd64 and riscv64 ✅

Flavor

• No changes between generic and aws ✅
• No changes between generic and azure ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅