pci_bridge_emul_confRegular
4.4: Absent ⚠️
4.8: Absent ⚠️
4.10: Absent ⚠️
4.13: Absent ⚠️
4.15: Absent ⚠️
4.18: Absent ⚠️
5.0: Absent ⚠️
5.3: Absent ⚠️
5.4: Absent ⚠️
5.8: Absent ⚠️
5.11: Absent ⚠️
5.13: Absent ⚠️
5.15: Absent ⚠️
5.19: Absent ⚠️
6.2: Absent ⚠️
6.5: Absent ⚠️
6.8: Absent ⚠️
arm64: ✅struct pci_bridge_emul_conf {
u16 vendor;
u16 device;
u16 command;
u16 status;
u32 class_revision;
u8 cache_line_size;
u8 latency_timer;
u8 header_type;
u8 bist;
u32 bar[2];
u8 primary_bus;
u8 secondary_bus;
u8 subordinate_bus;
u8 secondary_latency_timer;
u8 iobase;
u8 iolimit;
u16 secondary_status;
u16 membase;
u16 memlimit;
u16 pref_mem_base;
u16 pref_mem_limit;
u32 prefbaseupper;
u32 preflimitupper;
u16 iobaseupper;
u16 iolimitupper;
u8 capabilities_pointer;
u8 reserve[3];
u32 romaddr;
u8 intline;
u8 intpin;
u16 bridgectrl;
};
armhf: ✅struct pci_bridge_emul_conf {
u16 vendor;
u16 device;
u16 command;
u16 status;
u32 class_revision;
u8 cache_line_size;
u8 latency_timer;
u8 header_type;
u8 bist;
u32 bar[2];
u8 primary_bus;
u8 secondary_bus;
u8 subordinate_bus;
u8 secondary_latency_timer;
u8 iobase;
u8 iolimit;
u16 secondary_status;
u16 membase;
u16 memlimit;
u16 pref_mem_base;
u16 pref_mem_limit;
u32 prefbaseupper;
u32 preflimitupper;
u16 iobaseupper;
u16 iolimitupper;
u8 capabilities_pointer;
u8 reserve[3];
u32 romaddr;
u8 intline;
u8 intpin;
u16 bridgectrl;
};
ppc64el: Absent ⚠️
riscv64: Absent ⚠️
aws: Absent ⚠️
azure: Absent ⚠️
gcp: Absent ⚠️
lowlatency: Absent ⚠️
Arch