mcinfo_logical_cpuRegular
4.4: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
4.8: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
4.10: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
4.13: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
4.15: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
4.18: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.0: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.3: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.4: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.8: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.11: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.13: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.15: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
5.19: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
6.2: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
6.5: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
6.8: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
arm64: Absent ⚠️
armhf: Absent ⚠️
ppc64el: Absent ⚠️
riscv64: Absent ⚠️
aws: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
azure: Absent ⚠️
gcp: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
lowlatency: ✅struct mcinfo_logical_cpu {
uint32_t mc_cpunr;
uint32_t mc_chipid;
uint16_t mc_coreid;
uint16_t mc_threadid;
uint32_t mc_apicid;
uint32_t mc_clusterid;
uint32_t mc_ncores;
uint32_t mc_ncores_active;
uint32_t mc_nthreads;
uint32_t mc_cpuid_level;
uint32_t mc_family;
uint32_t mc_vendor;
uint32_t mc_model;
uint32_t mc_step;
char mc_vendorid[16];
char mc_brandid[64];
uint32_t mc_cpu_caps[7];
uint32_t mc_cache_size;
uint32_t mc_cache_alignment;
uint32_t mc_nmsrvals;
struct mcinfo_msr mc_msrvalues[8];
};
Regular
4.4 and 4.8 ✅
4.8 and 4.10 ✅
4.10 and 4.13 ✅
4.13 and 4.15 ✅
4.15 and 4.18 ✅
4.18 and 5.0 ✅
5.0 and 5.3 ✅
5.3 and 5.4 ✅
5.4 and 5.8 ✅
5.8 and 5.11 ✅
5.11 and 5.13 ✅
5.13 and 5.15 ✅
5.15 and 5.19 ✅
5.19 and 6.2 ✅
6.2 and 6.5 ✅
6.5 and 6.8 ✅
generic and aws ✅
generic and gcp ✅
generic and lowlatency ✅