website-struct

Struct: amd_iommu

Status

Regular

• In 4.4: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u8 *evt_buf;
      u8 *ppr_log;
      bool int_enabled;
      bool need_sync;
      struct device *iommu_dev;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
  };
  

• In 4.8: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u8 *evt_buf;
      u8 *ppr_log;
      bool int_enabled;
      bool need_sync;
      struct device *iommu_dev;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
  };
  

• In 4.10: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct device *iommu_dev;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      volatile u64 cmd_sem;
  };
  

• In 4.13: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      volatile u64 cmd_sem;
  };
  

• In 4.15: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
  };
  

• In 4.18: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
  };
  

• In 5.0: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
  };
  

• In 5.3: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In 5.4: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In 5.8: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In 5.11: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      u64 cmd_sem_val;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In 5.13: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      u64 cmd_sem_val;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In 5.15: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      u64 cmd_sem_val;
  };
  

• In 5.19: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      u64 cmd_sem_val;
  };
  

• In 6.2: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      u64 features2;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      struct amd_iommu_pci_seg *pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      u64 cmd_sem_val;
  };
  

• In 6.5: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      u64 features2;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      struct amd_iommu_pci_seg *pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      bool irtcachedis_enabled;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      atomic64_t cmd_sem_val;
  };
  

• In 6.8: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      u64 features2;
      u16 devid;
      u16 cap_ptr;
      struct amd_iommu_pci_seg *pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      unsigned char evt_irq_name[16];
      u8 *ppr_log;
      unsigned char ppr_irq_name[16];
      u8 *ga_log;
      unsigned char ga_irq_name[16];
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      bool irtcachedis_enabled;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 *cmd_sem;
      atomic64_t cmd_sem_val;
  };
  

Arch

• In arm64: Absent ⚠️
• In armhf: Absent ⚠️
• In ppc64el: Absent ⚠️
• In riscv64: Absent ⚠️

Flavor

• In aws: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In azure: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In gcp: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

• In lowlatency: ✅

  struct amd_iommu {
      struct list_head list;
      int index;
      raw_spinlock_t lock;
      struct pci_dev *dev;
      struct pci_dev *root_pdev;
      u64 mmio_phys;
      u64 mmio_phys_end;
      u8 *mmio_base;
      u32 cap;
      u8 acpi_flags;
      u64 features;
      bool is_iommu_v2;
      u16 devid;
      u16 cap_ptr;
      u16 pci_seg;
      u64 exclusion_start;
      u64 exclusion_length;
      u8 *cmd_buf;
      u32 cmd_buf_head;
      u32 cmd_buf_tail;
      u8 *evt_buf;
      u8 *ppr_log;
      u8 *ga_log;
      u8 *ga_log_tail;
      bool int_enabled;
      bool need_sync;
      struct iommu_device iommu;
      u32 stored_addr_lo;
      u32 stored_addr_hi;
      u32 stored_l1[108];
      u32 stored_l2[131];
      u8 max_banks;
      u8 max_counters;
      struct irq_domain *ir_domain;
      struct irq_domain *msi_domain;
      struct amd_irte_ops *irte_ops;
      u32 flags;
      volatile u64 cmd_sem;
      struct irq_affinity_notify intcapxt_notify;
  };
  

Differences

Regular

• No changes between 4.4 and 4.8 ✅
• Changed between 4.8 and 4.10 ⚠️

  • Field added. u8 *ga_log
  • Field added. u8 *ga_log_tail
  • Field added. struct amd_irte_ops *irte_ops
  • Field added. volatile u64 cmd_sem
• Changed between 4.10 and 4.13 ⚠️

  • Field added. u32 cmd_buf_head
  • Field added. u32 cmd_buf_tail
  • Field added. struct iommu_device iommu
  • Field removed. struct device *iommu_dev
• Changed between 4.13 and 4.15 ⚠️

  • Field added. u32 flags
• Changed between 4.15 and 4.18 ⚠️

  • Field type changed. spinlock_t lock ➡️ raw_spinlock_t lock
• No changes between 4.18 and 5.0 ✅
• Changed between 5.0 and 5.3 ⚠️

  • Field added. struct irq_affinity_notify intcapxt_notify
• No changes between 5.3 and 5.4 ✅
• No changes between 5.4 and 5.8 ✅
• Changed between 5.8 and 5.11 ⚠️

  • Field added. u64 cmd_sem_val
  • Field type changed. volatile u64 cmd_sem ➡️ volatile u64 *cmd_sem
• No changes between 5.11 and 5.13 ✅
• Changed between 5.13 and 5.15 ⚠️

  • Field removed. struct irq_affinity_notify intcapxt_notify
• No changes between 5.15 and 5.19 ✅
• Changed between 5.19 and 6.2 ⚠️

  • Field added. u64 features2
  • Field removed. struct irq_domain *msi_domain
  • Field type changed. u16 pci_seg ➡️ struct amd_iommu_pci_seg *pci_seg
• Changed between 6.2 and 6.5 ⚠️

  • Field added. bool irtcachedis_enabled
  • Field type changed. u64 cmd_sem_val ➡️ atomic64_t cmd_sem_val
• Changed between 6.5 and 6.8 ⚠️

  • Field added. unsigned char evt_irq_name[16]
  • Field added. unsigned char ppr_irq_name[16]
  • Field added. unsigned char ga_irq_name[16]
  • Field removed. bool is_iommu_v2

Arch

Flavor

• No changes between generic and aws ✅
• No changes between generic and azure ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅