DepSurf

Tracepoint: `qi_submit`

Status

Regular

In 4.4: Absent ⚠️
In 4.8: Absent ⚠️
In 4.10: Absent ⚠️
In 4.13: Absent ⚠️
In 4.15: Absent ⚠️
In 4.18: Absent ⚠️
In 5.0: Absent ⚠️
In 5.3: Absent ⚠️
In 5.4: Absent ⚠️
In 5.8: Absent ⚠️
In 5.11: Absent ⚠️

In 5.13: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

In 5.15: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

In 5.19: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

In 6.2: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

In 6.5: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

In 6.8: ✅

Event:

struct trace_event_raw_qi_submit {
    struct trace_entry ent;
    u64 qw0;
    u64 qw1;
    u64 qw2;
    u64 qw3;
    u32 __data_loc_iommu;
    char __data[0];
};

Function:

void trace_event_raw_event_qi_submit(void *__data, struct intel_iommu *iommu, u64 qw0, u64 qw1, u64 qw2, u64 qw3);

Arch

In arm64: Absent ⚠️
In armhf: Absent ⚠️
In ppc64el: Absent ⚠️
In riscv64: Absent ⚠️

Flavor

In aws: Absent ⚠️
In azure: Absent ⚠️
In gcp: Absent ⚠️
In lowlatency: Absent ⚠️

Differences

Regular

No changes between 5.13 and 5.15 ✅
No changes between 5.15 and 5.19 ✅
No changes between 5.19 and 6.2 ✅
No changes between 6.2 and 6.5 ✅
No changes between 6.5 and 6.8 ✅

DepSurf

Tracepoint: qi_submit

Status

Differences

Tracepoint: `qi_submit`