trace_event_data_offsets_xen_cpu_write_idt_entryRegular
4.4: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
4.8: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
4.10: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
4.13: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
4.15: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
4.18: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.0: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.3: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.4: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.8: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.11: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.13: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.15: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
5.19: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
6.2: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
6.5: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
6.8: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
arm64: Absent ⚠️
armhf: Absent ⚠️
ppc64el: Absent ⚠️
riscv64: Absent ⚠️
aws: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
azure: Absent ⚠️
gcp: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
lowlatency: ✅struct trace_event_data_offsets_xen_cpu_write_idt_entry {
};
Regular
4.4 and 4.8 ✅
4.8 and 4.10 ✅
4.10 and 4.13 ✅
4.13 and 4.15 ✅
4.15 and 4.18 ✅
4.18 and 5.0 ✅
5.0 and 5.3 ✅
5.3 and 5.4 ✅
5.4 and 5.8 ✅
5.8 and 5.11 ✅
5.11 and 5.13 ✅
5.13 and 5.15 ✅
5.15 and 5.19 ✅
5.19 and 6.2 ✅
6.2 and 6.5 ✅
6.5 and 6.8 ✅
generic and aws ✅
generic and gcp ✅
generic and lowlatency ✅