DepSurf

Struct: `tegra_clk_pll_params`

Status

Regular

In 4.4: Absent ⚠️
In 4.8: Absent ⚠️
In 4.10: Absent ⚠️
In 4.13: Absent ⚠️
In 4.15: Absent ⚠️
In 4.18: Absent ⚠️
In 5.0: Absent ⚠️
In 5.3: Absent ⚠️
In 5.4: Absent ⚠️
In 5.8: Absent ⚠️
In 5.11: Absent ⚠️
In 5.13: Absent ⚠️
In 5.15: Absent ⚠️
In 5.19: Absent ⚠️
In 6.2: Absent ⚠️
In 6.5: Absent ⚠️
In 6.8: Absent ⚠️

Arch

In arm64: Absent ⚠️

In armhf: ✅

struct tegra_clk_pll_params {
    long unsigned int input_min;
    long unsigned int input_max;
    long unsigned int cf_min;
    long unsigned int cf_max;
    long unsigned int vco_min;
    long unsigned int vco_max;
    u32 base_reg;
    u32 misc_reg;
    u32 lock_reg;
    u32 lock_mask;
    u32 lock_enable_bit_idx;
    u32 iddq_reg;
    u32 iddq_bit_idx;
    u32 reset_reg;
    u32 reset_bit_idx;
    u32 sdm_din_reg;
    u32 sdm_din_mask;
    u32 sdm_ctrl_reg;
    u32 sdm_ctrl_en_mask;
    u32 ssc_ctrl_reg;
    u32 ssc_ctrl_en_mask;
    u32 aux_reg;
    u32 dyn_ramp_reg;
    u32 ext_misc_reg[6];
    u32 pmc_divnm_reg;
    u32 pmc_divp_reg;
    u32 flags;
    int stepa_shift;
    int stepb_shift;
    int lock_delay;
    int max_p;
    bool defaults_set;
    const struct pdiv_map *pdiv_tohw;
    struct div_nmp *div_nmp;
    struct tegra_clk_pll_freq_table *freq_table;
    long unsigned int fixed_rate;
    u16 mdiv_default;
    u32 (*round_p_to_pdiv)(u32, u32 *);
    void (*set_gain)(struct tegra_clk_pll_freq_table *);
    int (*calc_rate)(struct clk_hw *, struct tegra_clk_pll_freq_table *, long unsigned int, long unsigned int);
    long unsigned int (*adjust_vco)(struct tegra_clk_pll_params *, long unsigned int);
    void (*set_defaults)(struct tegra_clk_pll *);
    int (*dyn_ramp)(struct tegra_clk_pll *, struct tegra_clk_pll_freq_table *);
};

In ppc64el: Absent ⚠️
In riscv64: Absent ⚠️

Flavor

In aws: Absent ⚠️
In azure: Absent ⚠️
In gcp: Absent ⚠️
In lowlatency: Absent ⚠️

Differences

Arch

DepSurf

Struct: tegra_clk_pll_params

Status

Differences

Struct: `tegra_clk_pll_params`