DepSurf

Struct: intel_iommu

Status

Regular

• In 4.4: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct device *iommu_dev;
      int node;
      u32 flags;
  };
  

• In 4.8: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct device *iommu_dev;
      int node;
      u32 flags;
  };
  

• In 4.10: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      u32 pasid_max;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct device *iommu_dev;
      int node;
      u32 flags;
  };
  

• In 4.13: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      u32 pasid_max;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 4.15: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      u32 pasid_max;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 4.18: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct pasid_entry *pasid_table;
      struct pasid_state_entry *pasid_state_table;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct idr pasid_idr;
      u32 pasid_max;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 5.0: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 5.3: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 5.4: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In 5.8: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
  };
  

• In 5.11: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
  };
  

• In 5.13: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
  };
  

• In 5.15: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct iopf_queue *iopf_queue;
      unsigned char iopfq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
      void *perf_statistic;
  };
  

• In 5.19: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct iopf_queue *iopf_queue;
      unsigned char iopfq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
      void *perf_statistic;
  };
  

• In 6.2: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      long unsigned int *copied_tables;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      long unsigned int prq_seq_number;
      struct completion prq_complete;
      struct ioasid_allocator_ops pasid_allocator;
      struct iopf_queue *iopf_queue;
      unsigned char iopfq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
      void *perf_statistic;
  };
  

• In 6.5: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u64 ecmdcap[4];
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      unsigned int perf_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      long unsigned int *copied_tables;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      long unsigned int prq_seq_number;
      struct completion prq_complete;
      struct iopf_queue *iopf_queue;
      unsigned char iopfq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
      void *perf_statistic;
      struct iommu_pmu *pmu;
  };
  

• In 6.8: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u64 vccap;
      u64 ecmdcap[4];
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      unsigned int perf_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      long unsigned int *copied_tables;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      long unsigned int prq_seq_number;
      struct completion prq_complete;
      struct iopf_queue *iopf_queue;
      unsigned char iopfq_name[16];
      struct q_inval *qi;
      u32 iommu_state[4];
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
      struct dmar_drhd_unit *drhd;
      void *perf_statistic;
      struct iommu_pmu *pmu;
  };
  

Arch

• In arm64: Absent ⚠️
• In armhf: Absent ⚠️
• In ppc64el: Absent ⚠️
• In riscv64: Absent ⚠️

Flavor

• In aws: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In azure: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In gcp: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

• In lowlatency: ✅

  struct intel_iommu {
      void *reg;
      u64 reg_phys;
      u64 reg_size;
      u64 cap;
      u64 ecap;
      u32 gcmd;
      raw_spinlock_t register_lock;
      int seq_id;
      int agaw;
      int msagaw;
      unsigned int irq;
      unsigned int pr_irq;
      u16 segment;
      unsigned char name[13];
      long unsigned int *domain_ids;
      struct dmar_domain ***domains;
      spinlock_t lock;
      struct root_entry *root_entry;
      struct iommu_flush flush;
      struct page_req_dsc *prq;
      unsigned char prq_name[16];
      struct q_inval *qi;
      u32 *iommu_state;
      struct ir_table *ir_table;
      struct irq_domain *ir_domain;
      struct irq_domain *ir_msi_domain;
      struct iommu_device iommu;
      int node;
      u32 flags;
  };
  

Differences

Regular

• No changes between 4.4 and 4.8 ✅
• Changed between 4.8 and 4.10 ⚠️

  • Field added. u32 pasid_max
• Changed between 4.10 and 4.13 ⚠️

  • Field added. struct iommu_device iommu
  • Field removed. struct device *iommu_dev
• No changes between 4.13 and 4.15 ✅
• No changes between 4.15 and 4.18 ✅
• Changed between 4.18 and 5.0 ⚠️

  • Field removed. struct pasid_entry *pasid_table
  • Field removed. struct pasid_state_entry *pasid_state_table
  • Field removed. struct idr pasid_idr
  • Field removed. u32 pasid_max
• No changes between 5.0 and 5.3 ✅
• No changes between 5.3 and 5.4 ✅
• Changed between 5.4 and 5.8 ⚠️

  • Field added. u64 vccap
  • Field added. struct completion prq_complete
  • Field added. struct ioasid_allocator_ops pasid_allocator
  • Field added. struct dmar_drhd_unit *drhd
• No changes between 5.8 and 5.11 ✅
• No changes between 5.11 and 5.13 ✅
• Changed between 5.13 and 5.15 ⚠️

  • Field added. struct iopf_queue *iopf_queue
  • Field added. unsigned char iopfq_name[16]
  • Field added. void *perf_statistic
• Changed between 5.15 and 5.19 ⚠️

  • Field removed. struct dmar_domain ***domains
• Changed between 5.19 and 6.2 ⚠️

  • Field added. long unsigned int *copied_tables
  • Field added. long unsigned int prq_seq_number
  • Field removed. struct irq_domain *ir_msi_domain
• Changed between 6.2 and 6.5 ⚠️

  • Field added. u64 ecmdcap[4]
  • Field added. unsigned int perf_irq
  • Field added. struct iommu_pmu *pmu
  • Field removed. struct ioasid_allocator_ops pasid_allocator
• Changed between 6.5 and 6.8 ⚠️

  • Field type changed. u32 *iommu_state ➡️ u32 iommu_state[4]

Arch

Flavor

• No changes between generic and aws ✅
• No changes between generic and azure ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅