DepSurf

Struct: dwc2_core_params

Status

Regular

• In 4.4: ✅

  struct dwc2_core_params {
      int otg_cap;
      int otg_ver;
      int dma_enable;
      int dma_desc_enable;
      int speed;
      int enable_dynamic_fifo;
      int en_multiple_tx_fifo;
      int host_rx_fifo_size;
      int host_nperio_tx_fifo_size;
      int host_perio_tx_fifo_size;
      int max_transfer_size;
      int max_packet_count;
      int host_channels;
      int phy_type;
      int phy_utmi_width;
      int phy_ulpi_ddr;
      int phy_ulpi_ext_vbus;
      int i2c_enable;
      int ulpi_fs_ls;
      int host_support_fs_ls_low_power;
      int host_ls_low_power_phy_clk;
      int ts_dline;
      int reload_ctl;
      int ahbcfg;
      int uframe_sched;
      int external_id_pin_ctl;
      int hibernation;
  };
  

• In 4.8: ✅

  struct dwc2_core_params {
      int otg_cap;
      int otg_ver;
      int dma_enable;
      int dma_desc_enable;
      int dma_desc_fs_enable;
      int speed;
      int enable_dynamic_fifo;
      int en_multiple_tx_fifo;
      int host_rx_fifo_size;
      int host_nperio_tx_fifo_size;
      int host_perio_tx_fifo_size;
      int max_transfer_size;
      int max_packet_count;
      int host_channels;
      int phy_type;
      int phy_utmi_width;
      int phy_ulpi_ddr;
      int phy_ulpi_ext_vbus;
      int i2c_enable;
      int ulpi_fs_ls;
      int host_support_fs_ls_low_power;
      int host_ls_low_power_phy_clk;
      int ts_dline;
      int reload_ctl;
      int ahbcfg;
      int uframe_sched;
      int external_id_pin_ctl;
      int hibernation;
  };
  

• In 4.10: ✅

  struct dwc2_core_params {
      int otg_cap;
      int otg_ver;
      int dma_desc_enable;
      int dma_desc_fs_enable;
      int speed;
      int enable_dynamic_fifo;
      int en_multiple_tx_fifo;
      int host_rx_fifo_size;
      int host_nperio_tx_fifo_size;
      int host_perio_tx_fifo_size;
      int max_transfer_size;
      int max_packet_count;
      int host_channels;
      int phy_type;
      int phy_utmi_width;
      int phy_ulpi_ddr;
      int phy_ulpi_ext_vbus;
      int i2c_enable;
      int ulpi_fs_ls;
      int host_support_fs_ls_low_power;
      int host_ls_low_power_phy_clk;
      int ts_dline;
      int reload_ctl;
      int ahbcfg;
      int uframe_sched;
      int external_id_pin_ctl;
      int hibernation;
      bool host_dma;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
  };
  

• In 4.13: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      bool hibernation;
      bool activate_stm_fs_transceiver;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 4.15: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      bool hibernation;
      bool activate_stm_fs_transceiver;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 4.18: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.0: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.3: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.4: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.8: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.11: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.13: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.15: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 5.19: ✅

  struct dwc2_core_params {
      struct usb_otg_caps otg_caps;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool activate_ingenic_overcurrent_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 6.2: ✅

  struct dwc2_core_params {
      struct usb_otg_caps otg_caps;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool activate_ingenic_overcurrent_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 6.5: ✅

  struct dwc2_core_params {
      struct usb_otg_caps otg_caps;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool activate_ingenic_overcurrent_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In 6.8: ✅

  struct dwc2_core_params {
      struct usb_otg_caps otg_caps;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool no_clock_gating;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool activate_stm_id_vb_detection;
      bool activate_ingenic_overcurrent_detection;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

Arch

• In arm64: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In armhf: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In ppc64el: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In riscv64: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

Flavor

• In aws: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In azure: Absent ⚠️
• In gcp: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

• In lowlatency: ✅

  struct dwc2_core_params {
      u8 otg_cap;
      u8 phy_type;
      u8 speed;
      u8 phy_utmi_width;
      bool phy_ulpi_ddr;
      bool phy_ulpi_ext_vbus;
      bool enable_dynamic_fifo;
      bool en_multiple_tx_fifo;
      bool i2c_enable;
      bool acg_enable;
      bool ulpi_fs_ls;
      bool ts_dline;
      bool reload_ctl;
      bool uframe_sched;
      bool external_id_pin_ctl;
      int power_down;
      bool lpm;
      bool lpm_clock_gating;
      bool besl;
      bool hird_threshold_en;
      bool service_interval;
      u8 hird_threshold;
      bool activate_stm_fs_transceiver;
      bool ipg_isoc_en;
      u16 max_packet_count;
      u32 max_transfer_size;
      u32 ahbcfg;
      u32 ref_clk_per;
      u16 sof_cnt_wkup_alert;
      bool host_dma;
      bool dma_desc_enable;
      bool dma_desc_fs_enable;
      bool host_support_fs_ls_low_power;
      bool host_ls_low_power_phy_clk;
      bool oc_disable;
      u8 host_channels;
      u16 host_rx_fifo_size;
      u16 host_nperio_tx_fifo_size;
      u16 host_perio_tx_fifo_size;
      bool g_dma;
      bool g_dma_desc;
      u32 g_rx_fifo_size;
      u32 g_np_tx_fifo_size;
      u32 g_tx_fifo_size[16];
      bool change_speed_quirk;
  };
  

Differences

Regular

• Changed between 4.4 and 4.8 ⚠️

  • Field added. int dma_desc_fs_enable
• Changed between 4.8 and 4.10 ⚠️

  • Field added. bool host_dma
  • Field added. bool g_dma
  • Field added. bool g_dma_desc
  • Field added. u32 g_rx_fifo_size
  • Field added. u32 g_np_tx_fifo_size
  • Field added. u32 g_tx_fifo_size[16]
  • Field removed. int dma_enable
• Changed between 4.10 and 4.13 ⚠️

  • Field added. bool activate_stm_fs_transceiver
  • Field added. bool change_speed_quirk
  • Field removed. int otg_ver
  • Field type changed. int otg_cap ➡️ u8 otg_cap
  • Field type changed. int dma_desc_enable ➡️ bool dma_desc_enable
  • Field type changed. int dma_desc_fs_enable ➡️ bool dma_desc_fs_enable
  • Field type changed. int speed ➡️ u8 speed
  • Field type changed. int enable_dynamic_fifo ➡️ bool enable_dynamic_fifo
  • Field type changed. int en_multiple_tx_fifo ➡️ bool en_multiple_tx_fifo
  • Field type changed. int host_rx_fifo_size ➡️ u16 host_rx_fifo_size
  • Field type changed. int host_nperio_tx_fifo_size ➡️ u16 host_nperio_tx_fifo_size
  • Field type changed. int host_perio_tx_fifo_size ➡️ u16 host_perio_tx_fifo_size
  • Field type changed. int max_transfer_size ➡️ u32 max_transfer_size
  • Field type changed. int max_packet_count ➡️ u16 max_packet_count
  • Field type changed. int host_channels ➡️ u8 host_channels
  • Field type changed. int phy_type ➡️ u8 phy_type
  • Field type changed. int phy_utmi_width ➡️ u8 phy_utmi_width
  • Field type changed. int phy_ulpi_ddr ➡️ bool phy_ulpi_ddr
  • Field type changed. int phy_ulpi_ext_vbus ➡️ bool phy_ulpi_ext_vbus
  • Field type changed. int i2c_enable ➡️ bool i2c_enable
  • Field type changed. int ulpi_fs_ls ➡️ bool ulpi_fs_ls
  • Field type changed. int host_support_fs_ls_low_power ➡️ bool host_support_fs_ls_low_power
  • Field type changed. int host_ls_low_power_phy_clk ➡️ bool host_ls_low_power_phy_clk
  • Field type changed. int ts_dline ➡️ bool ts_dline
  • Field type changed. int reload_ctl ➡️ bool reload_ctl
  • Field type changed. int ahbcfg ➡️ u32 ahbcfg
  • Field type changed. int uframe_sched ➡️ bool uframe_sched
  • Field type changed. int external_id_pin_ctl ➡️ bool external_id_pin_ctl
  • Field type changed. int hibernation ➡️ bool hibernation
• Changed between 4.13 and 4.15 ⚠️

  • Field added. bool oc_disable
• Changed between 4.15 and 4.18 ⚠️

  • Field added. bool acg_enable
  • Field added. int power_down
  • Field added. bool lpm
  • Field added. bool lpm_clock_gating
  • Field added. bool besl
  • Field added. bool hird_threshold_en
  • Field added. u8 hird_threshold
  • Field added. bool ipg_isoc_en
  • Field removed. bool hibernation
• Changed between 4.18 and 5.0 ⚠️

  • Field added. bool service_interval
  • Field added. u32 ref_clk_per
  • Field added. u16 sof_cnt_wkup_alert
• No changes between 5.0 and 5.3 ✅
• No changes between 5.3 and 5.4 ✅
• Changed between 5.4 and 5.8 ⚠️

  • Field added. bool activate_stm_id_vb_detection
• No changes between 5.8 and 5.11 ✅
• Changed between 5.11 and 5.13 ⚠️

  • Field added. bool no_clock_gating
• No changes between 5.13 and 5.15 ✅
• Changed between 5.15 and 5.19 ⚠️

  • Field added. struct usb_otg_caps otg_caps
  • Field added. bool activate_ingenic_overcurrent_detection
  • Field removed. u8 otg_cap
• No changes between 5.19 and 6.2 ✅
• No changes between 6.2 and 6.5 ✅
• No changes between 6.5 and 6.8 ✅

Arch

• No changes between amd64 and arm64 ✅
• No changes between amd64 and armhf ✅
• No changes between amd64 and ppc64el ✅
• No changes between amd64 and riscv64 ✅

Flavor

• No changes between generic and aws ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅