dw_pcie_rp
Regular
4.4
: Absent ⚠️
4.8
: Absent ⚠️
4.10
: Absent ⚠️
4.13
: Absent ⚠️
4.15
: Absent ⚠️
4.18
: Absent ⚠️
5.0
: Absent ⚠️
5.3
: Absent ⚠️
5.4
: Absent ⚠️
5.8
: Absent ⚠️
5.11
: Absent ⚠️
5.13
: Absent ⚠️
5.15
: Absent ⚠️
5.19
: Absent ⚠️
6.2
: ✅struct dw_pcie_rp {
bool has_msi_ctrl;
bool cfg0_io_shared;
u64 cfg0_base;
void *va_cfg0_base;
u32 cfg0_size;
resource_size_t io_base;
phys_addr_t io_bus_addr;
u32 io_size;
int irq;
const struct dw_pcie_host_ops *ops;
int msi_irq[8];
struct irq_domain *irq_domain;
struct irq_domain *msi_domain;
dma_addr_t msi_data;
struct irq_chip *msi_irq_chip;
u32 num_vectors;
u32 irq_mask[8];
struct pci_host_bridge *bridge;
raw_spinlock_t lock;
long unsigned int msi_irq_in_use[4];
};
6.5
: ✅struct dw_pcie_rp {
bool has_msi_ctrl;
bool cfg0_io_shared;
u64 cfg0_base;
void *va_cfg0_base;
u32 cfg0_size;
resource_size_t io_base;
phys_addr_t io_bus_addr;
u32 io_size;
int irq;
const struct dw_pcie_host_ops *ops;
int msi_irq[8];
struct irq_domain *irq_domain;
struct irq_domain *msi_domain;
dma_addr_t msi_data;
struct irq_chip *msi_irq_chip;
u32 num_vectors;
u32 irq_mask[8];
struct pci_host_bridge *bridge;
raw_spinlock_t lock;
long unsigned int msi_irq_in_use[4];
};
6.8
: ✅struct dw_pcie_rp {
bool has_msi_ctrl;
bool cfg0_io_shared;
u64 cfg0_base;
void *va_cfg0_base;
u32 cfg0_size;
resource_size_t io_base;
phys_addr_t io_bus_addr;
u32 io_size;
int irq;
const struct dw_pcie_host_ops *ops;
int msi_irq[8];
struct irq_domain *irq_domain;
struct irq_domain *msi_domain;
dma_addr_t msi_data;
struct irq_chip *msi_irq_chip;
u32 num_vectors;
u32 irq_mask[8];
struct pci_host_bridge *bridge;
raw_spinlock_t lock;
long unsigned int msi_irq_in_use[4];
};
arm64
: Absent ⚠️
armhf
: Absent ⚠️
ppc64el
: Absent ⚠️
riscv64
: Absent ⚠️
aws
: Absent ⚠️
azure
: Absent ⚠️
gcp
: Absent ⚠️
lowlatency
: Absent ⚠️
Regular
6.2
and 6.5
✅
6.5
and 6.8
✅