DepSurf

Struct: `dw_pcie`

Status

Regular

In 4.4: Absent ⚠️
In 4.8: Absent ⚠️
In 4.10: Absent ⚠️

In 4.13: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
};

In 4.15: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
};

In 4.18: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
};

In 5.0: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
};

In 5.3: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In 5.4: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In 5.8: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In 5.11: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    bool iatu_unroll_enabled;
    bool io_cfg_atu_shared;
};

In 5.13: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    bool iatu_unroll_enabled;
    bool io_cfg_atu_shared;
};

In 5.15: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    bool iatu_unroll_enabled;
    bool io_cfg_atu_shared;
};

In 5.19: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    bool iatu_unroll_enabled;
    bool io_cfg_atu_shared;
};

In 6.2: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    u32 region_align;
    u64 region_limit;
    struct dw_pcie_rp pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    u32 version;
    u32 type;
    long unsigned int caps;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    struct clk_bulk_data app_clks[3];
    struct clk_bulk_data core_clks[4];
    struct reset_control_bulk_data app_rsts[3];
    struct reset_control_bulk_data core_rsts[7];
    struct gpio_desc *pe_rst;
};

In 6.5: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    u32 region_align;
    u64 region_limit;
    struct dw_pcie_rp pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    u32 version;
    u32 type;
    long unsigned int caps;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    struct dw_edma_chip edma;
    struct clk_bulk_data app_clks[3];
    struct clk_bulk_data core_clks[4];
    struct reset_control_bulk_data app_rsts[3];
    struct reset_control_bulk_data core_rsts[7];
    struct gpio_desc *pe_rst;
};

In 6.8: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    size_t atu_size;
    u32 num_ib_windows;
    u32 num_ob_windows;
    u32 region_align;
    u64 region_limit;
    struct dw_pcie_rp pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    u32 version;
    u32 type;
    long unsigned int caps;
    int num_lanes;
    int link_gen;
    u8 n_fts[2];
    struct dw_edma_chip edma;
    struct clk_bulk_data app_clks[3];
    struct clk_bulk_data core_clks[4];
    struct reset_control_bulk_data app_rsts[3];
    struct reset_control_bulk_data core_rsts[7];
    struct gpio_desc *pe_rst;
    bool suspended;
};

Arch

In arm64: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In armhf: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In ppc64el: Absent ⚠️

In riscv64: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

Flavor

In aws: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In azure: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In gcp: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

In lowlatency: ✅

struct dw_pcie {
    struct device *dev;
    void *dbi_base;
    void *dbi_base2;
    void *atu_base;
    u32 num_viewport;
    u8 iatu_unroll_enabled;
    struct pcie_port pp;
    struct dw_pcie_ep ep;
    const struct dw_pcie_ops *ops;
    unsigned int version;
};

Differences