DepSurf

Function: vlbr_exclude_host

Status

Regular

• In 4.4: Absent ⚠️
• In 4.8: Absent ⚠️
• In 4.10: Absent ⚠️
• In 4.13: Absent ⚠️
• In 4.15: Absent ⚠️
• In 4.18: Absent ⚠️
• In 5.0: Absent ⚠️
• In 5.3: Absent ⚠️
• In 5.4: Absent ⚠️
• In 5.8: Absent ⚠️
• In 5.11: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81014fc9)
  Location: arch/x86/events/intel/lbr.c:746
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 5.13: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff810161c9)
  Location: arch/x86/events/intel/lbr.c:762
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 5.15: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81017c29)
  Location: arch/x86/events/intel/lbr.c:762
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 5.19: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81019c33)
  Location: arch/x86/events/intel/lbr.c:741
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 6.2: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101dc63)
  Location: arch/x86/events/intel/lbr.c:681
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 6.5: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101d963)
  Location: arch/x86/events/intel/lbr.c:681
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

• In 6.8: Full Inline ⚠️

  Collision: Unique Static

  Inline: Full

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81023a33)
  Location: arch/x86/events/intel/lbr.c:700
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_read
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_disable_all
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_enable_all
  

Arch

• In arm64: Absent ⚠️
• In armhf: Absent ⚠️
• In ppc64el: Absent ⚠️
• In riscv64: Absent ⚠️

Flavor

• In aws: Absent ⚠️
• In azure: Absent ⚠️
• In gcp: Absent ⚠️
• In lowlatency: Absent ⚠️

Differences