uv_setup_irq
Regular
4.4
: Absent ⚠️
4.8
: Absent ⚠️
4.10
: Absent ⚠️
4.13
: Absent ⚠️
4.15
: Absent ⚠️
4.18
: Absent ⚠️
5.0
: Absent ⚠️
5.3
: Absent ⚠️
5.4
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff81098580)
Location: arch/x86/platform/uv/uv_irq.c:184
Inline: False
Symbols:
ffffffff81098580-ffffffff810986fa: uv_setup_irq (STB_GLOBAL)
5.8
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff8109dd70)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff8109dd70-ffffffff8109dee4: uv_setup_irq (STB_GLOBAL)
5.11
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff81099940)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff81099940-ffffffff81099ab7: uv_setup_irq (STB_GLOBAL)
5.13
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff8109a150)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff8109a150-ffffffff8109a2c4: uv_setup_irq (STB_GLOBAL)
5.15
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff810aa170)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff810aa170-ffffffff810aa315: uv_setup_irq (STB_GLOBAL)
5.19
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff810bfbb0)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff810bfbb0-ffffffff810bfd8b: uv_setup_irq (STB_GLOBAL)
6.2
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff810dbaa0)
Location: arch/x86/platform/uv/uv_irq.c:185
Inline: False
Symbols:
ffffffff810dbaa0-ffffffff810dbc7b: uv_setup_irq (STB_GLOBAL)
6.5
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff810e7050)
Location: arch/x86/platform/uv/uv_irq.c:184
Inline: False
Symbols:
ffffffff810e7050-ffffffff810e724f: uv_setup_irq (STB_GLOBAL)
6.8
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff810ef400)
Location: arch/x86/platform/uv/uv_irq.c:184
Inline: False
Symbols:
ffffffff810ef400-ffffffff810ef5ff: uv_setup_irq (STB_GLOBAL)
arm64
: Absent ⚠️
armhf
: Absent ⚠️
ppc64el
: Absent ⚠️
riscv64
: Absent ⚠️
aws
: Absent ⚠️
azure
: Absent ⚠️
gcp
: Absent ⚠️
lowlatency
: ✅int uv_setup_irq(char *irq_name, int cpu, int mmr_blade, long unsigned int mmr_offset, int limit);
Collision: Unique Global
Inline: No
Transformation: False
Instances:
In arch/x86/platform/uv/uv_irq.c (ffffffff81099a50)
Location: arch/x86/platform/uv/uv_irq.c:184
Inline: False
Symbols:
ffffffff81099a50-ffffffff81099bca: uv_setup_irq (STB_GLOBAL)
Regular
5.4
and 5.8
✅
5.8
and 5.11
✅
5.11
and 5.13
✅
5.13
and 5.15
✅
5.15
and 5.19
✅
5.19
and 6.2
✅
6.2
and 6.5
✅
6.5
and 6.8
✅
generic
and lowlatency
✅