DepSurf

Function: p4_pmu_disable_event

Status

Regular

• In 4.4: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81012310)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81012310-ffffffff81012335: p4_pmu_disable_event (STB_LOCAL)
  

• In 4.8: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81011e07)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81011d10-ffffffff81011d35: p4_pmu_disable_event (STB_LOCAL)
  

• In 4.10: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81011f37)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81011e40-ffffffff81011e65: p4_pmu_disable_event (STB_LOCAL)
  

• In 4.13: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81010653)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81010440-ffffffff81010465: p4_pmu_disable_event (STB_LOCAL)
  

• In 4.15: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81011203)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81011250-ffffffff81011275: p4_pmu_disable_event (STB_LOCAL)
  

• In 4.18: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff810119f1)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81011980-ffffffff810119a5: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.0: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81012041)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81012080-ffffffff810120a5: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.3: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff810133c1)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013400-ffffffff81013425: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.4: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81013b71)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013bb0-ffffffff81013bd5: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.8: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff810151a1)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81015310-ffffffff81015335: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.11: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81015641)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff810157b0-ffffffff810157d5: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.13: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff810168d1)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81016910-ffffffff81016935: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.15: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff810183db)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81018420-ffffffff81018445: p4_pmu_disable_event (STB_LOCAL)
  

• In 5.19: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff8101a53b)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff8101a5a0-ffffffff8101a5de: p4_pmu_disable_event (STB_LOCAL)
  

• In 6.2: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff8101e65b)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff8101e6d0-ffffffff8101e70e: p4_pmu_disable_event (STB_LOCAL)
  

• In 6.5: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff8101e349)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff8101e3c0-ffffffff8101e3fe: p4_pmu_disable_event (STB_LOCAL)
  

• In 6.8: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81024409)
  Location: arch/x86/events/intel/p4.c:904
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81024480-ffffffff810244be: p4_pmu_disable_event (STB_LOCAL)
  

Arch

• In arm64: Absent ⚠️
• In armhf: Absent ⚠️
• In ppc64el: Absent ⚠️
• In riscv64: Absent ⚠️

Flavor

• In aws: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81013b71)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013bb0-ffffffff81013bd5: p4_pmu_disable_event (STB_LOCAL)
  

• In azure: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81013030)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013080-ffffffff810130b1: p4_pmu_disable_event (STB_LOCAL)
  

• In gcp: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81013b31)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013b70-ffffffff81013b95: p4_pmu_disable_event (STB_LOCAL)
  

• In lowlatency: Selective Inline ⚠️

  void p4_pmu_disable_event(struct perf_event *event);
  

  Collision: Unique Static

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/p4.c (ffffffff81013d51)
  Location: arch/x86/events/intel/p4.c:903
  Inline: True
  Inline callers:
    - arch/x86/events/intel/p4.c:p4_pmu_disable_all
  

  Symbols:

  ffffffff81013d90-ffffffff81013db5: p4_pmu_disable_event (STB_LOCAL)
  

Differences

Regular

• No changes between 4.4 and 4.8 ✅
• No changes between 4.8 and 4.10 ✅
• No changes between 4.10 and 4.13 ✅
• No changes between 4.13 and 4.15 ✅
• No changes between 4.15 and 4.18 ✅
• No changes between 4.18 and 5.0 ✅
• No changes between 5.0 and 5.3 ✅
• No changes between 5.3 and 5.4 ✅
• No changes between 5.4 and 5.8 ✅
• No changes between 5.8 and 5.11 ✅
• No changes between 5.11 and 5.13 ✅
• No changes between 5.13 and 5.15 ✅
• No changes between 5.15 and 5.19 ✅
• No changes between 5.19 and 6.2 ✅
• No changes between 6.2 and 6.5 ✅
• No changes between 6.5 and 6.8 ✅

Arch

Flavor

• No changes between generic and aws ✅
• No changes between generic and azure ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅