DepSurf

Function: lbr_from_signext_quirk_wr

Status

Regular

• In 4.4: Absent ⚠️
• In 4.8: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff810111cf)
  Location: arch/x86/events/intel/lbr.c:270
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff81010ff0-ffffffff81011018: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 4.10: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101131c)
  Location: arch/x86/events/intel/lbr.c:270
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff81011150-ffffffff81011178: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 4.13: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8100f9a7)
  Location: arch/x86/events/intel/lbr.c:270
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff8100f7f0-ffffffff8100f818: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 4.15: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101007c)
  Location: arch/x86/events/intel/lbr.c:274
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff8100ff90-ffffffff8100ffb8: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 4.18: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81010a1c)
  Location: arch/x86/events/intel/lbr.c:274
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff81010910-ffffffff81010938: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.0: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81011014)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff81010ef0-ffffffff81010f18: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.3: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff810123e7)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff810122d0-ffffffff810122f2: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.4: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81012b97)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff81012a80-ffffffff81012aa2: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.8: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81014352)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:__intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:__intel_pmu_lbr_restore
  

  Symbols:

  ffffffff81014500-ffffffff81014522: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.11: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81013f7f)
  Location: arch/x86/events/intel/lbr.c:330
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  

  Symbols:

  ffffffff810143f0-ffffffff81014412: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.13: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101513f)
  Location: arch/x86/events/intel/lbr.c:330
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  

  Symbols:

  ffffffff81015550-ffffffff81015572: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.15: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101676f)
  Location: arch/x86/events/intel/lbr.c:330
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  

  Symbols:

  ffffffff81016b70-ffffffff81016b8f: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 5.19: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101899f)
  Location: arch/x86/events/intel/lbr.c:309
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff81018e80-ffffffff81018eb3: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 6.2: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101c81f)
  Location: arch/x86/events/intel/lbr.c:249
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff8101cd80-ffffffff8101cdb3: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 6.5: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8101c4df)
  Location: arch/x86/events/intel/lbr.c:249
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff8101ca40-ffffffff8101ca73: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In 6.8: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff8102246f)
  Location: arch/x86/events/intel/lbr.c:249
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_arch_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_restore
  Direct callers:
    - arch/x86/events/intel/core.c:check_msr
    - arch/x86/events/intel/core.c:check_msr
  

  Symbols:

  ffffffff810229d0-ffffffff81022a03: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

Arch

• In arm64: Absent ⚠️
• In armhf: Absent ⚠️
• In ppc64el: Absent ⚠️
• In riscv64: Absent ⚠️

Flavor

• In aws: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81012b97)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff81012a80-ffffffff81012aa2: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In azure: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81011b0b)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff810119f0-ffffffff81011a12: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In gcp: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81012b57)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff81012a40-ffffffff81012a62: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

• In lowlatency: Selective Inline ⚠️

  u64 lbr_from_signext_quirk_wr(u64 val);
  

  Collision: Unique Global

  Inline: Selective

  Transformation: False

  Instances:

  In arch/x86/events/intel/lbr.c (ffffffff81012d77)
  Location: arch/x86/events/intel/lbr.c:279
  Inline: True
  Inline callers:
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
    - arch/x86/events/intel/lbr.c:intel_pmu_lbr_sched_task
  

  Symbols:

  ffffffff81012c60-ffffffff81012c82: lbr_from_signext_quirk_wr (STB_GLOBAL)
  

Differences

Regular

• No changes between 4.8 and 4.10 ✅
• No changes between 4.10 and 4.13 ✅
• No changes between 4.13 and 4.15 ✅
• No changes between 4.15 and 4.18 ✅
• No changes between 4.18 and 5.0 ✅
• No changes between 5.0 and 5.3 ✅
• No changes between 5.3 and 5.4 ✅
• No changes between 5.4 and 5.8 ✅
• No changes between 5.8 and 5.11 ✅
• No changes between 5.11 and 5.13 ✅
• No changes between 5.13 and 5.15 ✅
• No changes between 5.15 and 5.19 ✅
• No changes between 5.19 and 6.2 ✅
• No changes between 6.2 and 6.5 ✅
• No changes between 6.5 and 6.8 ✅

Arch

Flavor

• No changes between generic and aws ✅
• No changes between generic and azure ✅
• No changes between generic and gcp ✅
• No changes between generic and lowlatency ✅